Digital Systems Laboratory Lab 3: Combinational Logic Design with Decoders and Multiplexers Objectives To design a combinational
Question:
Digital Systems Laboratory   
Lab 3: Combinational Logic Design with Decoders and Multiplexers 
Objectives
 To design a combinational circuit and implement it with decoders.
 To design a combinational circuit and implement it with multiplexers.
Apparatus
7404 HEX inverter
7430 8 input NAND gate (x2)
74151 8x1 multiplexer
74154 4to16 line decoder
PreLab Questions:
 Design a parity generator by using a 74151 multiplexer. Parity (P) is an extra bit that is added to ensure that the number of bits with the value one in a set of bits is even or odd. For odd parity, the parity bit is set if number of ones in the code is even, otherwise it set to 0. Fill the parity bit (P) column in Table 1 for a 4bit code (A, B, C, D). Assume odd parity method as it is explained before.
 Table 1
Inputs  Parity Bit  
A  B  C  D  P 
0  0  0  0  
0  0  0  1  
0  0  1  0  
0  0  1  1  
0  1  0  0  
0  1  0  1  
0  1  1  0  
0  1  1  1  
1  0  0  0  
1  0  0  1  
1  0  1  0  
1  0  1  1  
1  1  0  0  
1  1  0  1  
1  1  1  0  
1  1  1  1 

 Design the parity bit generator circuit defined in Q1. The circuit has four inputs (A, B, C, D) and one output (P). Use one 4 lineto1 line multiplexer and external gates (if required) in the design.
 Hint: If you choose A and B as selection bits, then inputs of the multiplexer will be a function of C and D.
 Design a combinational logic circuit by using one 74154 decoder and only NAND gates. The circuit has 2bit inputs, A and B, and two outputs Z1 and Z2. The circuit operates as follows:
 If A+B is EVEN, Z1Z2=01
 If A+B is ODD, Z1Z2=10
Digital Systems Laboratory   
 Design the logic circuit defined in Q3 by using 3to8 line decoders and external logic gates.
 Test all the designs in Q1, Q2, Q3 and Q4 with the digital circuit simulator Proteus ISIS before lab session, and send the files to your lab assistant.
IC Description:
74151 is a 8 lineto1 line multiplexer. It has the schematic representation shown in Fig 1. Selection lines A, B and C select the particular input and this input is directed to the output. Strobe S acts as an enable signal. If S =1, the 74151 is disabled and output Y = 0. If S = 0 then the 74151 is enabled and it functions as a multiplexer. Table 2 shows the multiplex function of 74151 in terms of select lines.
Table 2
Figure 1
74154 is a 4 lineto16 line decoder. Fig.2 shows the pinout for the 74154. This IC decodes four binarycoded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. The function table of IC 74154 is given Table 3.
Figure 2
Digital Systems Laboratory   
Table 3
Procedure:
 Connect the parity generator circuit that you designed in the prelab Q1 and verify the operation of the circuit. Connect an LED to the multiplexer output to observe the state of the parity bit for all possible input combinations..
 Connect the logic circuit that you designed in the prelab Q3 and test the circuit by applying all possible input combinations.
Finite Mathematics and Its Applications
ISBN: 9780134768632
12th edition
Authors: Larry J. Goldstein, David I. Schneider, Martha J. Siegel, Steven Hair