$1.$ For a direct$-$mapped cache design with a $64-$bit address, the following bits of the address are used to access the cache.

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$1\mathrm{.}1$ What is the cache block size $($in words$)?$

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$1\mathrm{.}2$ How many blocks does the cache have?

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$1\mathrm{.}3$ What is the ratio between total bits required for such a cache implementation over the data storage bits?

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Beginning from power on$,$ the following byte$-$addressed cache references are recorded.

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$1\mathrm{.}4$ For each reference, list $(1)$ its tag, index, and offset, $(2)$ whether it is a hit or a miss, and $(3)$ which bytes were replaced $($if any$).$

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$1\mathrm{.}5$ What is the hit ratio?