1. Instruction Decoder (20 points). When an instruction is executed by a processor, the instruction is decoded into a set of control signals that are used to control the various processor components (e.g., register file, ALU) and data path. This decoding task can be implemented using either a ROM or decoders. You are asked to implement such a decoder for a simplified MIPS instruction set, called mini-MIPS. Mini-MIPS uses 5 bit opcode (01-05) and supports 13 instructions. The table below shows all the 13 instructions and their opcodes. For each instruction, the table also lists the corresponding values of eight control signals. Please design a decoder for mini-MIPS using decoders and gates and show your logic circuits schematic (Hint: use decoders and logical gates). Instruction 05 04 03 02 01 Immed_en WE LD_enable ST_enable als 1 1 0 10 LW 1 1 0 0 0 0 SW 1 0 0 0 0 0 ADDI 0 1 0 0 0 1 SUBI 0 1 0 0 1 1 ADD 0 1 0 1 0 0 SUB 0 1 0 1 1 0 AND 0 1 1 0 0 0 OR 0 1 1 0 1 0 XOR 0 1 1 1 0 0 NOR 0 1 1 1 1 0 0 0 0 0 0 0 BEQ 0 0 0 1 0 0 | BNEQ000OOO Msel bneq/beq 100 11 00 0 0 0 0 0 1 0 0 0 10 00 00 0 0 0 00 0 0 0 010 0 0 1 0 0 0 | 1 0 0 0 10 0 0 0 0 0 0 0 0 0 05 04 03 02 011 Immed_en WE LD_enable ST_enable Msel bneq/beq 1. Instruction Decoder (20 points). When an instruction is executed by a processor, the instruction is decoded into a set of control signals that are used to control the various processor components (e.g., register file, ALU) and data path. This decoding task can be implemented using either a ROM or decoders. You are asked to implement such a decoder for a simplified MIPS instruction set, called mini-MIPS. Mini-MIPS uses 5 bit opcode (01-05) and supports 13 instructions. The table below shows all the 13 instructions and their opcodes. For each instruction, the table also lists the corresponding values of eight control signals. Please design a decoder for mini-MIPS using decoders and gates and show your logic circuits schematic (Hint: use decoders and logical gates). Instruction 05 04 03 02 01 Immed_en WE LD_enable ST_enable als 1 1 0 10 LW 1 1 0 0 0 0 SW 1 0 0 0 0 0 ADDI 0 1 0 0 0 1 SUBI 0 1 0 0 1 1 ADD 0 1 0 1 0 0 SUB 0 1 0 1 1 0 AND 0 1 1 0 0 0 OR 0 1 1 0 1 0 XOR 0 1 1 1 0 0 NOR 0 1 1 1 1 0 0 0 0 0 0 0 BEQ 0 0 0 1 0 0 | BNEQ000OOO Msel bneq/beq 100 11 00 0 0 0 0 0 1 0 0 0 10 00 00 0 0 0 00 0 0 0 010 0 0 1 0 0 0 | 1 0 0 0 10 0 0 0 0 0 0 0 0 0 05 04 03 02 011 Immed_en WE LD_enable ST_enable Msel bneq/be