1. [M, None, 7.4] Figure 1 shows a practical implementation of a pulse register. Clock Clk is ideal with 50% duty cycle. X D- Clkd CIk Figure 0.1 Pulse register. Data : Vpp = 2.5V, tp an = 200ps, node capacitances are Ccia= 10ff, C= 10ff, both true and complementary outputs node capacitances are 20fF. a. Draw the waveforms at nodes Clk, Clkd, X and Q for two clock cycles, with D=0 in one cycle and D = 1 in the other. b. What is the approximate value of setup and hold times for this circuit? c. c)If the probability that D will change its logic value in one clock cycle is a, with equal probability of being 0 or 1, what is the power consumption of this circuit? (exclude the power consumption in the clock line) fe= 100 MHz. . O 10