$1$ Objective

The basic requirement of the project is to design a very simple CPU which uses a

microsequencer in the Control Path. The individual components of the CPU must be

implemented in Verilog. Component interconnections and simple mapping logic can be realized

directly in the Block Diagram$/$Schematic File design file$($s$).$

$2$ Requirements

The CPU must implement the following functions: LOAD, STORE, ADD, SUBTRACT, and

JUMP. The CPU must implement also at least one of the following bullets:

PSHA and PULLA; where PSHA will decrement SP and push $[$A$]$ to the address m$[$SP$]$;

PULLA will read the contents of the address $m[SP]$ to A and increment $SP$;

implementation of these instructions will require introduction of the Stack Pointer $($SP$)$

register;

JEQ $ZZ==$PClarr