1. Problem: Implement a twos-complement 4-bit ripple-carry adder/subtractor. (using LogicWorks)

Procedure:

a. Following the instruction How to create an independent part from bottom to up using LogicWorks, create a 1-bit full adder device and save it into a library.

b. By using 4 of the 1-bit full adder device created into the library in Step.1 (together with some logic gates), implement a 4-bit adder/subtractor to perform X Y , where X = X3X2 X1X0 and Y = Y3Y2Y1Y0 . The inputs to the adder/subtractor are X, Y and C0 , and the outputs from the adder/subtractor are the sum bits S = S3S2S1S0 , an overflow flag v, a carry-out flag c, a zero flag z, a negative flag n, and an odd-sum-parity flag o. The flags are defined as the following:

overflow flag v: if there is an overflow, then v = 1, otherwise v = 0;

carry-out flag c: if C4 =1, then c = 1, otherwise c = 0;

zero flag z: if the sum output = 0, then z = 1, otherwise z = 0;

negative flag n: if the sum output < 0, then n = 1, otherwise n = 0;

odd-sum-parity flag o: if the sum output is odd, then o = 1, otherwise o = 0.

c. Include a clock in your circuit, but do not connect it with any part of the circuit (we are not using the clock as an input signal but only a time measurement of other signals). Set the clock low and high parameters as 10 and 10, and label the clock output as CLK so that the clock signal will show in the simulation.

d. Simulate the addition and subtraction operations by following the procedures specified below. Organize your signals in the simulation so that the signals appear from top-to-bottom in the order of CLK, v, c, z, n, o, S3, S2, S1, S0, X3, X2, X1, X0, Y3, Y2, Y1, Y0, C0 . The C0 input controls the add/sub operations.