1. The following timing diagram is from a clocked sequential circuit. clk in state output SO...

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1. The following timing diagram is from a clocked sequential circuit. clk in state output SO S1 S2 S1 S2 1. Determine if it is likely a Mealy or Moore circuit 2. Determine the functional input/output pairs 3. If the timing diagram were to show the last clock cycle, what would be the next state? 4. The timing diagram "walks" through every arc of the FSM. Draw the FSM diagram. 1. The following timing diagram is from a clocked sequential circuit. clk in state output SO S1 S2 S1 S2 1. Determine if it is likely a Mealy or Moore circuit 2. Determine the functional input/output pairs 3. If the timing diagram were to show the last clock cycle, what would be the next state? 4. The timing diagram "walks" through every arc of the FSM. Draw the FSM diagram.