$1.$ The generator to be implemented has two inputs, X$1$ and X$2,$ and the output Y $.$ The output is set to logic level $1$ during a certain number of clock signal cycles; this number is specified by the bits applied to both inputs. Thus: $$ if X$2$X$1=01,$ Y $=1$ for one cycle;$$ if X$2$X$1=10,$ Y $=1$ for two cycles;$$ if X$2$X$1=11,$ Y $=1$ for three cycles. Draw the state diagram and implement this FSM using D flip flop