1. The Single-cycle Datapath shown below has 11 separate busses that are identified (A) to (K) (some repeated for clarity). In this problem you are to identify which busses with be "actively involved" for various kinds of instructions 125:0Shift Jump 32 left 2 28 0 26 PC+4131:28] Add H) Shift (C)left2 4 Control Branch Unit MemtoReg [31:26] ALUSrS ovf zero MemW 25Read Addri Instruction Memory Address 1[31:0] Register Read (A) Read Addr 2 Data1 Address [20:16] Data File Write Addr Write Data ALU Data Memory Out Read Datal 0 Data MemRead [15:0] 16 Sign 32 Extend ALUMI (D) ontrol ALUO [5:0] a. List all of the busses that are "actively" involved with an "slti" instruction: b. List all of the busses that are "actively" involved with an "beq" instruction that passes: C. List all of the busses that are "actively" involved with an "lui" instruction: d. List all of the busses that are "actively" involved with an "xor" instruction: e. List all of the busses that are "actively" involved with an "lw" instruction: f. List all of the busses that are "actively" involved with an "j" instruction: g. List all of the busses that are "actively" involved with an "sltu" instruction: h. List all of the busses that are "actively" involved with an "sw" instruction: i. List all of the busses that are "actively" involved with an "beq" instruction that fails: j. List all of the busses that are "actively" involved with an "addi" instruction 1. The Single-cycle Datapath shown below has 11 separate busses that are identified (A) to (K) (some repeated for clarity). In this problem you are to identify which busses with be "actively involved" for various kinds of instructions 125:0Shift Jump 32 left 2 28 0 26 PC+4131:28] Add H) Shift (C)left2 4 Control Branch Unit MemtoReg [31:26] ALUSrS ovf zero MemW 25Read Addri Instruction Memory Address 1[31:0] Register Read (A) Read Addr 2 Data1 Address [20:16] Data File Write Addr Write Data ALU Data Memory Out Read Datal 0 Data MemRead [15:0] 16 Sign 32 Extend ALUMI (D) ontrol ALUO [5:0] a. List all of the busses that are "actively" involved with an "slti" instruction: b. List all of the busses that are "actively" involved with an "beq" instruction that passes: C. List all of the busses that are "actively" involved with an "lui" instruction: d. List all of the busses that are "actively" involved with an "xor" instruction: e. List all of the busses that are "actively" involved with an "lw" instruction: f. List all of the busses that are "actively" involved with an "j" instruction: g. List all of the busses that are "actively" involved with an "sltu" instruction: h. List all of the busses that are "actively" involved with an "sw" instruction: i. List all of the busses that are "actively" involved with an "beq" instruction that fails: j. List all of the busses that are "actively" involved with an "addi" instruction