$1.)$ This adder requires two CLC levels and

five carry$-$lookahead circuits CLCs

$2.)$ The $2$nd level CLC uses the group P and G outputs from the four $1$st level CLCs as inputs and provides the carry outputs C$4,$ C$8,$ and C$12.$

$3.)$ The P and G group outputs from the $2$nd level CLC cover carry generation and propagation for all $16$ bits and by using an OC circuit, we can combine these two outputs with C$0$ to produce carry C$16$

Now $,$ assuming that each passage through CLC block requires two gate delays, the delay of this circuit can be estimated as

$5$ x $2=10$ gate delays compared to

$2$ x $16+2=34$ gate delays for the $16-$bit ripple carry adder.

Therefore performance improves by a factor greater than three.

The formula for the maximum delay of a CLA using L CLC levels $=2$L $1$

for L levels.