$1.$ This exercise refers to the files:

XOR$2$gate.sv

XOR$2$gate testbench.sv

a$.$ After loading these fies into the EDA playground, run a simulation and include a timing diagram of your simulation in your report.

b$.$ Edit the design file and convert the Verilog code to a behavioral model that performs the same function as the structural model. After doing this, run a simulation and include your code and a timing diagram of your simulation in your report.

XOR testbench:reg x$1,$ x$2$;

reg y$1$;

$//$display variables

initial

$monitor $("$x$1=\%$b$,$ x$2=\%$b$,$ y$1=\%$b$",$ x$1,$ x$2,$ y$1)$;

$//$instantiate the xor$2$input module into the test bench

xor$2$input XOR$2\_$SIM $($

$.$x$1($x$1),$

$.$x$2($x$2),$

$.$y$1($y$1)$

$)$;

$//$apply input vectors

initial begin

$//$ Dump waves

$dumpfile$("$dump$.$vcd$")$;

$dumpvars$(1,$ xor$2\_$tb$)$;

#$0$ x$1=1\text{'}$b$0$;

x$2=1\text{'}$b$0$;

#$1$ x$1=1\text{'}$b$0$;

x$2=1\text{'}$b$1$;

#$1$ x$1=1\text{'}$b$1$;

x$2=1\text{'}$b$0$;

#$1$ x$1=1\text{'}$b$1$;

x$2=1\text{'}$b$1$;

#$10$ $stop;

end

endmodule

XOR sv:module xor$2$input $($x$1,$ x$2,$ y$1)$;

input x$1,$ x$2$;

output y$1$;

wire x$1$not, x$2$not, a$1,$ a$2$;

not inv$1($x$1$not, x$1)$;

not inv$2($x$2$not, x$2)$;

and and$1($a$1,$ x$2,$ x$1$not$)$;

and and$2($a$2,$ x$1,$ x$2$not$)$;

or or$1($y$1,$ a$1,$ a$2)$;

endmodule

$2.$ This exercise refers to the files:

full adder $1$bit behavioral model.sv

full adder $1$bit behavioral model testbench.sv

a$.$ After loading these files into the EDA playground, run a simulation and include a timing diagram of your simulation in your report.

b$.$ Edit the test bench file in order to add two more test cases to your simulation after those already shown in your timing diagram $($you may choose the time at which to initiate these values$)$:

i$.$ a $=1$; b $=1$; c $=1$;

ii$.$ a $=1$; b $=0$; c $=0$;

$3.$ This exercise refers to the files:

full adder $4$bit ripple carry behavioral model.sv

full adder $4$bit ripple carry behavioral model testbench.sv

a$.$ After loading these files into the EDA playground, run a simulation and include a timing diagram of your simulation in your report.

b$.$ Edit the design and test bench files in order to convert the $4-$bit adder into an $8-$bit adder. Choose four different pairs of values for the a and b operands $($with cin $=0).$

i$.$ Run a simulation and include your code and a timing diagram of your simulation in your report.

ii$.$ For the four sets of values you chose, verify $\text{'}$by hand' the addition took place correctly by comparing your timing diagram results with the answers you computed by hand. Make sure to refer to the timing diagram in your report in order to show exactly where your predicted result is computed.