$1)$ UART baud$-$rate mismatch

Assume that your sender clock is precisely at the specified value $($exactly $20\mathrm{.}0000000$ MHz$,$

or whatever$),$ divided down to exactly $9600\mathrm{.}0000$ baud $($or whatever$)$ exactly $16\mathrm{.}00000$

samples per bit. Determine both how fast and how slow the receiver clock can run for the

system to still work. Use our classroom assumptions that the $$start of the start$$ is the

fist low bit followed by $2-$out$-$of$-3$ of samples $3,5,$ and $7$ being low. Assume that samples

$8,9,$ and $10($out of $16,$ numbered $1-16)$ are used to determine the data value. Since this

is also $2-$out$-$of$-3$ voting, you can detect the proper value if only $2$ of those samples are

still within the correct bit $($time$).$ Since the allowed amount of clock drift will vary with

how many bits are sent after re$-$synching, work this for both the $10$ bit $(1$ start bit, $8$ data

bits, one stop bit$)$ and $11$ bit $(...9$ data bits $..)$ cases. $($So$,$ you$$ve got $4$ total sets of

numbers to crunch once you set up the problem$).$ Express your answer as a percentage

of the sender$$s clock $($so$,$ don$$t actually use the $20\mathrm{.}0000000$ and $9600\mathrm{.}000$ above in your

answer, or even in your problem for that matter$).$ The hardest part is probably deciding

where to $$draw the line$$ and count in order to determine the ratio of received bits to sent

bits. You want this to be as late as possible $($e$.$g$.$ as long after the start bit as possible$).$