$1-$ Use the following code fragment:

Assume that the initial value of R $4$ is $\backslash (\backslash$mathrm$\{$R$\}2+792\backslash ).$

For this exercise assume the standard DLX integer pipeline $($as shown in Figure $3\mathrm{.}10)$ and the standard DLX FP pipeline as described in Figures $3\mathrm{.}43$ and $3\mathrm{.}44.$ If structural hazards are due to write$-$back contention, assume the earliest instruction gets priority and other instructions are stalled.

a Show the timing of this instruction sequence for the DLX FP pipeline without any forwarding or bypassing hardware but assuming a register read and a write in the same clock cycle "forwards" through the register file, as in Figure $3\mathrm{.}10.$ Use a pipeline timing chart like Figure $3\mathrm{.}14$ or $3\mathrm{.}15.$ Assume that the branch is handled by flushing the pipeline. If all memory references hit in the cache, how many cycles does this loop take to execute?

b Show the timing of this instruction sequence for the DLX FP pipeline with normal forwarding and bypassing hardware. Use a pipeline timing chart like Figure $3\mathrm{.}14$ or $3\mathrm{.}15.$ Assume that the branch is handled by predicting it as not taken. If all memory references hit in the cache, how many cycles does this loop take to execute?

c Assuming the DLX FP pipeline with a single$-$cycle delayed branch and full bypassing and forwarding hardware, schedule the instructions in the loop including the branch$-$delay slot. You may reorder instructions and modify the individual instruction operands, but do not undertake other loop transformations that change the number or opcode of the instructions in the loop $($that$\text{'}$s for the next chapter!$).$ Show a pipeline timing diagram and compute the time needed in cycles to execute the entire loop.