$1.$ Using ChatGPT: Generate Verilog codes for a simple CPU with a $5-8$ instructions.

Report the screenshot of the prompts and the generated code.

$2.$ Create a SystemVerilog testbench to functionally test the above CPU as shown in image with the following features: a$.$ At the TOP: interface, testbench and CPU must be instantiated

b$.$ Testbench should be implemented as program and contain the above

interface

c$.$ Testbench program should be connected to CPU module in the TOP module using the above interface $($CPU can have interface or it can be a purely Verilog model with ports$).$

d$.$ The interface should have synchronous signals defined with respect to a clocking block

e$.$ Clock should be generated in the module TOP

f$.$ A coverage model should be defined for the CPU $($you may define coverpoints and bins appropriately$)$

g$.$ The testbench program should generate random stimuli