1. We’ve added the reset signal as an additional input to the module in the header. However, when will this occur? Will it be synchronous, i.e. synchronised with the clock edge, or will it be asynchronous, i.e. it can happen any time regardless of the value of clock? You have a think.

2. Can you explain what is this code about? Thank you.

3. What is blocking and non-blocking assignment? Whats the difference and their importance?

3. What are the resources to practice on Verilog? Can you also recommend resources for me to practice on hardware designing?

 

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module updatedfred (input clock, enable, reset, output reg [3:0] count, output wire always (posedge clock) if (reset) count module updatedfred (input clock, enable, reset, output reg [3:0] count, output wire always (posedge clock) if (reset) count