$1)$What are the address bits that represent the system ID field?$2)$What are the address bits that represent the system decoding field?$3)$What is the size of each chip in RAM$3$ module?$4)$What is the size of each chip in ROM$2$ module?$5)$Are Both ROM$1$ and RAM$1$ can access at the same time. but with read only in ROM $?6)$Are This design can represent with $3$X$8$ active high decoder without changes in output gates $?7)$What is the size of each chip in ROM$1$ module?$8)$Is Q$7-$output is can be connected to I$/$O devices $?9)$Q$0$ can connect to both chips in ROM$1?10)$One of them is correct about I$/$O mapped devices instead memory mapped $-$I$/$O mapped needs fewer address lines$-$I$/$O mapped needs a bigger buffer space than memory mapped $-$none$-$I$/$O mapped produces faster transfer of data$11)$What is end address hex range of ROM$2$ module?