Question: 1. What is the difference between Dataflow modelling and Behavioural modelling in VHDL? (Mention at least 5 differences) 2. What is Structural modelling in VHDL?
1. What is the difference between Dataflow modelling and Behavioural modelling in VHDL? (Mention at least 5 differences)
2. What is Structural modelling in VHDL? What are its advantages?
3. Write a VHDL code to implement a basic 4:1Multiplexer:

Do 4 D1 D2 D3 Si S0
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