1. Write an entitylarchitecture pair for a generic 2-digit Binary Coded Decimal counter The range of the counter is set by the MIN and MAX generics. Upon RESET, or whenever CLEAR is asserted, the counter is set to the MIN value. The counter will increment whenever ENABLE is asserted and it will automatically roll over from the MAX value to the MIN value. The TERM output is asserted whenever the counter is at its MAX value (50 pts) The architecture should be named RTL and the entity should match the following: entity BCD-COUNTER is generic ( MAX : natural range to 99 : 10; : natural range to 99 := ); Maximum count value before rollover MIN -Value used for CLEAR and rollover port RESET:in std_logic CLOCK : in std_logic ENABLE in std_logic CLEAR : in std_logic TERM: out std_logic COUNT : out std-logic-vector (7 downto )); .. Count value Active high master reset Master clock Counter clock enable Counter synchronous clear Counter roll over indicator end entity; 1. Write an entitylarchitecture pair for a generic 2-digit Binary Coded Decimal counter The range of the counter is set by the MIN and MAX generics. Upon RESET, or whenever CLEAR is asserted, the counter is set to the MIN value. The counter will increment whenever ENABLE is asserted and it will automatically roll over from the MAX value to the MIN value. The TERM output is asserted whenever the counter is at its MAX value (50 pts) The architecture should be named RTL and the entity should match the following: entity BCD-COUNTER is generic ( MAX : natural range to 99 : 10; : natural range to 99 := ); Maximum count value before rollover MIN -Value used for CLEAR and rollover port RESET:in std_logic CLOCK : in std_logic ENABLE in std_logic CLEAR : in std_logic TERM: out std_logic COUNT : out std-logic-vector (7 downto )); .. Count value Active high master reset Master clock Counter clock enable Counter synchronous clear Counter roll over indicator end entity