1. Write VHDL code to describe the circuit shown below (just write the architecture part including internal signal declarations; no entity part is needed). E B D D D clk 9 C Y 2. For each process below, classify the process as combinational or sequential, and draw a circuit schematic. You can use any basic gates, muxes, adders, subtractors, decoders, flip flops/registers, etc. (a) In this module, signal S is a 2-bit std_logic_vector and signals A, B, and Y are 4-bit signed. is process (A, B, S) begin if S= "00 then Y