1) Write VHDL descriptions for components that implement the following functions Note that each component will have in inputs A, B, C, and D, and a single output, F1 (or F2, F3, F4). FI(A,B,C,D)-1 ifand only if all inputs (A, B, C, and D are1 or all inputs are 0 FAA,B,C,D)-'1' if and only if two of the inputs = "1 F3(A,B,C,D) = "I' if and only if the number of inputs that = '1, is odd. FAA,B,C,D) = m(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) F1 F2 AB AB CD 00 0 10 CD 00 0 0 01 10 10 F3 F4 AB AB CD00 0 0 CD 00 0 10 01 01 10 10 1) Write VHDL descriptions for components that implement the following functions Note that each component will have in inputs A, B, C, and D, and a single output, F1 (or F2, F3, F4). FI(A,B,C,D)-1 ifand only if all inputs (A, B, C, and D are1 or all inputs are 0 FAA,B,C,D)-'1' if and only if two of the inputs = "1 F3(A,B,C,D) = "I' if and only if the number of inputs that = '1, is odd. FAA,B,C,D) = m(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) F1 F2 AB AB CD 00 0 10 CD 00 0 0 01 10 10 F3 F4 AB AB CD00 0 0 CD 00 0 10 01 01 10 10