$(1)$ XOR $74\_86,(1)$ NOT $74\_04,(1)4-$bit adder $74\_283,(1)$ Quad $2-$input mux$74\_157$Now your task is to combine what you did in Tasks $1$ and $2$ to build a circuit that has four modes, determined by two select switches $($S$1,$ S$0)$:$(0,0)$ no change$(0,1)$ negate input in sign$-$magnitude form$(1,0)$ negate input in $1$s complement form$(1,1)$ negate input in $2$s complement form Notice in this scheme that the S$1$ value determines which general group is selected $($Task $1$ or Task $2$ functions$)$ and the S$0$ value determines which function within those groups is selected $(1$s comp vs$.2$s comp; No change vs$.$ Sign$-$Magnitude$).$ Therefore, the S$0$ switch serves the same purpose as the individual select switch already used in both Task $1$ and Task $2.$But that S$1$ value needs a new device to allow it to select. That new device, unsurprisingly, is a data selector $($or multiplexer, or mux$).$ The mux IC available in our lab is the $74\_157,$ which performs selection between two $4-$bit numbers.Looking at the device symbol:This mux should always be enabled, so what logic value should be passed to the EN port?When SEL$=1,$ the input bits labeled with a $1($such as D$1)$ are those that make it to the corresponding output bit $($such as QD$)$When SEL$=0,$ the input bits labeled with a $0$ are selectedKnowing this $($and the mode definitions$),$ you have two big questions to answer:oWhat should be connected to the $0$ inputs $($the outputs from Task $1$ or Task $2)?$oWhich select switch $($S$1$ or S$0)$ should be connected to the SEL input?In LogicWorks, use the chip schematics to simulate and test your design.