10. You are given the information that a particular program has stride 10 in an 8-way interleaved memory system and a bank cycle time of 5 clock periods after an access occurs. Complete the following table Memory word index Bank accessed Clock cycle when accessed 8001 8011 8021 8031 8041 8051 8061 8071 8081 8091 8101 8111 3 4 Verify that, for a stream of addresses with stride 10, each access to bank 1 after the first one is delayed by 2 clock periods. Also verify that the average access time is 1.5 clock periods per memory access 1. Design a 2-way set-associative cache with 16-byte cache lines and a data capacity of 16 kB (kilobytes) 2. For the cache that you designed in Problem 3, find the values of c, d, and s, as defined on p. 35 of the slides on hierarchical memory Also find the number of bits in the tag, index and byte offset fields, assuming 32-bit addressing. How do the values change when going to 64 bit addressing 10. You are given the information that a particular program has stride 10 in an 8-way interleaved memory system and a bank cycle time of 5 clock periods after an access occurs. Complete the following table Memory word index Bank accessed Clock cycle when accessed 8001 8011 8021 8031 8041 8051 8061 8071 8081 8091 8101 8111 3 4 Verify that, for a stream of addresses with stride 10, each access to bank 1 after the first one is delayed by 2 clock periods. Also verify that the average access time is 1.5 clock periods per memory access 1. Design a 2-way set-associative cache with 16-byte cache lines and a data capacity of 16 kB (kilobytes) 2. For the cache that you designed in Problem 3, find the values of c, d, and s, as defined on p. 35 of the slides on hierarchical memory Also find the number of bits in the tag, index and byte offset fields, assuming 32-bit addressing. How do the values change when going to 64 bit addressing