Data Path Cycles: Use the following data to answer the questions below: Instruction Memory: 150 ps...

  

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Data Path Cycles: Use the following data to answer the questions below: Instruction Memory: 150 ps Data Memory: Stage 1 Stage 4 Stage 3 Stage 2 and 5 Assume that mux, control unit, PC accesses, sign extension unit and wires have no latency. 250 ps 100 ps 50 ps ALU and adders: Register File: R 1. Using the datapath diagram determine the time that each of the types of instructions would require. Load Store BEQ JUMP 2. If every instruction executes in I clock cycle of a fixed length, what is the length of one clock cycle? 3. If every instruction executes in I clock cycle using a variable length clock (no pipelining), with an instruction mix of 15% loads, 25% stores, 45% ALU type, 11% branches and 4% jumps, what is the average length clock cycle? R = Load = 4. If the datapath is evaluated by letting each stage of execution determine the cycle time, which allows us to use a pipelined design, how many stages are used by each type of instruction? Store = BEQ = JUMP %3D 5. In order to use a pipelined design for the datapath, what would be the length of a cycle (in ps)? 6. Using a pipelined design and the above mix of instructions, where a jump always causes a 1 cycle delay, 30% of the load instructions are immediately followed by an instruction that uses the result (causing a l-cyle delay), and 15% of the branch instructions are misdirected (causing a 2-cycle delay). What is the average effective number of cycles once the pipeline is loaded? Data Path Cycles: Use the following data to answer the questions below: Instruction Memory: 150 ps Data Memory: Stage 1 Stage 4 Stage 3 Stage 2 and 5 Assume that mux, control unit, PC accesses, sign extension unit and wires have no latency. 250 ps 100 ps 50 ps ALU and adders: Register File: R 1. Using the datapath diagram determine the time that each of the types of instructions would require. Load Store BEQ JUMP 2. If every instruction executes in I clock cycle of a fixed length, what is the length of one clock cycle? 3. If every instruction executes in I clock cycle using a variable length clock (no pipelining), with an instruction mix of 15% loads, 25% stores, 45% ALU type, 11% branches and 4% jumps, what is the average length clock cycle? R = Load = 4. If the datapath is evaluated by letting each stage of execution determine the cycle time, which allows us to use a pipelined design, how many stages are used by each type of instruction? Store = BEQ = JUMP %3D 5. In order to use a pipelined design for the datapath, what would be the length of a cycle (in ps)? 6. Using a pipelined design and the above mix of instructions, where a jump always causes a 1 cycle delay, 30% of the load instructions are immediately followed by an instruction that uses the result (causing a l-cyle delay), and 15% of the branch instructions are misdirected (causing a 2-cycle delay). What is the average effective number of cycles once the pipeline is loaded?

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