12 marks) (b) A synchronous state sequencer that has two cycles (odd and even) is to be designed. The even cycle sequences 0, 2, 4, 6 and repeats while the odd cycle sequences 1, 3, 5, 7 and repeats. An external input Y selects which cycle to perform. An input of Y = 0 selects the even cycle and an input of Y = 1 selects the odd cycle. The even cycle can only be entered and exited through state 0 and the odd cycle through state 1. Obtain the Moore Model state diagram for the specification above and show the implementation of the circuit using FPGA by writing a Verilog code including its test bench. 42 markal 12 marks) (b) A synchronous state sequencer that has two cycles (odd and even) is to be designed. The even cycle sequences 0, 2, 4, 6 and repeats while the odd cycle sequences 1, 3, 5, 7 and repeats. An external input Y selects which cycle to perform. An input of Y = 0 selects the even cycle and an input of Y = 1 selects the odd cycle. The even cycle can only be entered and exited through state 0 and the odd cycle through state 1. Obtain the Moore Model state diagram for the specification above and show the implementation of the circuit using FPGA by writing a Verilog code including its test bench. 42 markal