18.What technique allows you bypass the CPU when transferring data from main memory to an I/O device.

19. The line size of a cache chunk is usually between ????? and ?????? bytes

20. The LMC instruction 392 performs what type of function?

21.If you have a true color display using 8 bits for the intensity of each primary color. How many colors can you create for the display

22. Name the fastest type of cache memory in a computer architecture is ????? 23. In a RISC architecture all the opcodes are of the same ???????

24. In a SMP system it is important to maintain cache coherency since multiple processors are accessing a common memory. Listening for cache events on the memory bus shared by multiple processors is referred to as ?????????????

24. When one instruction can prematurely access data from a register that is being acted upon by a previous instruction, this creates a pipeline event known as a data ?????????????.

25. A ?????????????? cache delays writing the changes to RAM until absolutely necessary