1-re-write the VHDL. If you faced some errors for a specific reason, please fix it. 2-synthesize it and provide the synthesized circuit. 3-do simulation and provide the waveform 4-Briefly, explain the functionality of each program.

library ieee; use ieee.std_logic_1164.all: entity multiplexer_2 2x is port( x y: in std_logic_vector (7 downto 0); s: in std_logic: f: out std_logic_vector( 7 downto 0) ): end entity; architecture logic_flow of multiplexer_2 21 is begin f