$2=0\mathrm{.}18,L_{\text{m}\text{i}\text{n}}=2,W_{\text{m}\text{i}\text{n}}=4$

Draw a $1-$bit full adder $($FA$),2-$input NAND, and $2-$input AND cells using MAGIC, make sure it passes all DRCs$,$ extract the circuit level netlist, and simulate its behaviour using SPICE. $(2$ points each: $6$ points total$)$

Use hierarchical design flow to instantiate cells from Q$1$ to create CSA$-$W $($white$)$ and CSA$-$G $($grey$)$ cells shown on slide$-3,$ make sure it passes all DRCs$,$ extract the circuit level netlist, and simulate their behaviour using SPICE. $(2$ points each: $4$ points total$)$

Use hierarchical design flow to instantiate CSA$-$W $($white$),$ CSA$-$G $($grey$),$ and FA cells from Q$2$ and flip$-$flops from DE$-5,$ to create a $2$bit Baugh$-$Wooley signed multiplier shown on slide$-4.$ Make sure it passes all DRCs$,$ extract the circuit level netlist. $(10$ points$).$

Perform SPICE simulation and plot inputs and outputs for $(2$ points each: $8$ points total$)$

a$.00(2$ points$)$

b$.11(2$ points$)$

c$.1-1(2$ points$)$

d$.-2x-1(2$ points$)$

Find the maximum clock frequency using SPICE. $(2$ points$).$