$(20$ points$)9\mathrm{.}7.$ One of the most critical etching steps in the CMOS process flow is etching the polysilicon gates. Suppose in a particular process, the manufacturing control on the polysilicon gate thickness is $\backslash (3500\backslash$AA $\backslash$pm $500\backslash$AA $\backslash ).$ Suppose also that a $\backslash (10\backslash \%\backslash )$ overetch has to be done because the etching rate itself can vary by $\backslash (\backslash$pm $10\backslash \%\backslash ).$ The gate oxide in this process is $\backslash (15\backslash$AA $\backslash )$ thick. The etching process is allowed to etch through the gate oxide and into the silicon source drain regions, but not deeper than $\backslash (100\backslash$AA $\backslash )$ into the silicon. Assuming that the poly and the silicon etch at the same rate, what is the minimum required selectivity in the etching process between poly and oxide?