$20$ points

Consider the LE from a cyclone IV FPGA shown in Figure $4.$ Cyclone IV LE can perform one combinational and$/$or registered function which can involve up to four variables. According to the datasheet, it has the timing specifications given in Table $1.$

Figure $4$: Cyclone IV Logic Element $($LE$)$

Table $1$: Timing specification for Cyclone IV FPGA

$\backslash$table$[[$Name$,$Value $($ps$)],[t_{\text{p}\text{e}\text{q}},t_{ccq},199],[t_{\text{s}\text{e}\text{t}\text{u}\text{p}},76],[t_{\text{h}\text{o}\text{l}\text{d}},0],[t_{pd}($per LE$),381],[t_{\text{w}\text{i}\text{r}\text{e}}($between LEs$),246],[t_{\text{s}\text{k}\text{e}\text{w}},0]]$

$($a$)$ What is the minimum number of Cyclone IV LEs required to implement the FSM of Figure $5?$

$($b$)$ Without clock skew, what is the fastest clock frequency at which this FSM will run reliably?

$($c$)$ With $0\mathrm{.}3$ ns of clock skew, what is the fastest frequency at which the FSM will run reliably?