Question: ( 2 0 points ) Define the module for the given logic circuit? module AeqB ( output input J not Go ( _ _ )

(20 points) Define the module for the given logic circuit?
module AeqB ( output input
J
not Go (__) ;
not G1:
and GL (- ; ;
or G4(-:-;
endmodule
(5 points) Fill in the blank with the name of the Verilog function, syntax and description is given:
$ ("text_with_format_specifiers", list_of_arguments) ;
prints the formatted message whenever one of the arguments changes.
(10 points)2Yx=101, Draw the path from F to input and find the value of F :
(10 points) instantiate the module AeqB() inside the testbench module.
??testbench
timescale 1ns1ns
module tbAeqB;??reg for inputs
reg??wire for outputs
()
(10 points) Fill the Karnaugh map for the truth table in question 5.
Write the simplified logical expression:
\table[[x,Y,Z,F
( 2 0 points ) Define the module for the given

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