$(20$ points$)$ Problem $5\mathrm{.}28$ on the textbook. You are not required to submit simulation plots.

But you should clearly show the counting sequence starting with $001$ at time $0$ in your answer. With blocking assignments this code produces the desired logic function, which is $\backslash ($ f$=\backslash )\backslash ($ a$\_\{1\}$ a$\_\{0\}+\backslash$cdots$+$a$\_\{$n$-1\}$ a$\_\{$n$-2\}\backslash ).$ What logic function is produced if we change the code to use non$-$blocking assignments?

$5\mathrm{.}28$ The Verilog code in Figure P$5\mathrm{.}9$ represents a $3-$bit linear$-$feedback shift register $($LFSR$).$ This type of circuit generates a counting sequence of pseudo$-$random numbers that repeats after $\backslash (2^\{$n$\}-1\backslash )$ clock cycles, where $\backslash ($ n $\backslash )$ is the number of flip$-$flops in the LFSR$.$ Synthesize a circuit to implement the LFSR in a chip. Draw a diagram of the circuit. Simulate the circuit's behavior by loading the pattern $001$ into the LFSR and then enabling the register to count. What is the counting sequence?

$```$

module lfsr $($R$,$ L$,$ Clock, Q$)$;

input $[0$:$2]$ R;

input L$,$ Clock;

output reg $[0$:$2]$ Q;

always @$($posedge Clock$)$

if $($L$)$

QR;

else

QQ$[2],$ Q$[0]^$ Q$[2],$ Q$[1]\}$;

endmodule

$```$

Figure P$5\mathrm{.}9$ Code for a linear$-$feedback shift register.