2.)

1) Pipelining and data hazards a) Assume a 7 stage, scalar (1-wide) in-order MIPS pipeline with stages: FT, FA, D, E, MT, MA, W Aside: while not germane to this problem, assume that each memory stage has been split in two for serialized tag check and data access in the l and D caches] Assume full forwarding and bypass networks. Indicate stalled instruction occupancy in a pipeline stage with a lower case letter (ft,fa,d,e,mt,ma,w). Assume that all hazard detection and bubble insertion logic is in decode (D). Indicate, by drawing a vertical arrow when a value is bypassed from one instruction to another in the cycle that the forwarding occurs. For simplicity, elide WD bypassing arrows. Assume that all loads and stores are hits and that there are no exceptions. Assume that there are zero branch delay slots and perfect branch prediction Consider the following sequence of instructions (you may assume them to be the inner body of a FOR loop with the initialization code elided) scheduled on the above pipeline, if the next dynamic instance of the instruction at label I will be a taken branch A: w $2, 40 ($6) B: lw $2, 0 ($2) C: lw $3, 40 (S7) D lw $3, 0 ($3) E add $3, $3, $2 F Sw $3, 0 ($2) G addi S6, 6, -64 H addi $7, $7, -64 Ibeq $6, $5, A Build a table where there is one row for each dynamic instruction and one column for each cycle, starting with the tag check on the fetch of the instruction at label A. Fill in the table with the stage currently occupied by the instruction in that row in that cycle until the instruction beq instruction reaches the writeback stage b) Assuming that all registers other than 0 (fixed), 1 (reserved), 5 (input), 6 (input), and 7(input) and 31(reserved) are freely available for use and that the above sequence can be unrolled by 2x, unroll the above loop and schedule 2 iterations on the same pipeline. What is the improvement in cycles/iteration? 1) Pipelining and data hazards a) Assume a 7 stage, scalar (1-wide) in-order MIPS pipeline with stages: FT, FA, D, E, MT, MA, W Aside: while not germane to this problem, assume that each memory stage has been split in two for serialized tag check and data access in the l and D caches] Assume full forwarding and bypass networks. Indicate stalled instruction occupancy in a pipeline stage with a lower case letter (ft,fa,d,e,mt,ma,w). Assume that all hazard detection and bubble insertion logic is in decode (D). Indicate, by drawing a vertical arrow when a value is bypassed from one instruction to another in the cycle that the forwarding occurs. For simplicity, elide WD bypassing arrows. Assume that all loads and stores are hits and that there are no exceptions. Assume that there are zero branch delay slots and perfect branch prediction Consider the following sequence of instructions (you may assume them to be the inner body of a FOR loop with the initialization code elided) scheduled on the above pipeline, if the next dynamic instance of the instruction at label I will be a taken branch A: w $2, 40 ($6) B: lw $2, 0 ($2) C: lw $3, 40 (S7) D lw $3, 0 ($3) E add $3, $3, $2 F Sw $3, 0 ($2) G addi S6, 6, -64 H addi $7, $7, -64 Ibeq $6, $5, A Build a table where there is one row for each dynamic instruction and one column for each cycle, starting with the tag check on the fetch of the instruction at label A. Fill in the table with the stage currently occupied by the instruction in that row in that cycle until the instruction beq instruction reaches the writeback stage b) Assuming that all registers other than 0 (fixed), 1 (reserved), 5 (input), 6 (input), and 7(input) and 31(reserved) are freely available for use and that the above sequence can be unrolled by 2x, unroll the above loop and schedule 2 iterations on the same pipeline. What is the improvement in cycles/iteration