2. (12 points) A memory system has 48 bits virtual address and 36 bits physical address. The page size is 4 KB. The cache is 128 KB 2-way set associative with 32 bytes per block and is physically addressed. The figure below shows the TLB translation and the addressing of the cache. Name each of the fields and indicate how many bits are needed, use the table: Virtual address field bits TUB name block offset tag Physical address physical page number page offset virtual page number index D E F to the cache