2. (15 points) Assume a memory system with 32-bit address space that is byte addressable. A data word in such a system consists of 4-bytes (32-bits). Assume you want to design a 256KB two-way set associative cache with sixteen (16) data words per cache block. Answer the following questions (b) (2 points) What is the total number of bits needed to implement the cache if it has a valid and a dirty bit field (in additional data and tag fields). Show your work. (c) (3 points) Show the design of the cache using block diagrams only (similar to figure on page 773 of textbook #1). (d) Identify which set (index) each of the following byte addresses maps into: 124, 128, 68, 262212, 262230. Show your work. (e) (4 points) Assume an initially empty cache, identify whether each of the following memory references results in a hit or miss: 124, 128, 68, 262212, 262230, 124. Assume LRU replacement policy. (f) (2 points) Show the final content of the cache (only show sets that are of interest and byte address ranges in each cache block as appropriate)