$2.(25\text{'})1).$ Different logic families could be mixed to achieve desired logic functions. A CMOS$/$transmission$-$gate hybrid circuit is shown in Figure $1.$ In it$,$ A and B are inputs, and F is the output. Can you identify the logic function $\backslash ((\backslash$mathrm$\{$F$\}=\backslash )?)$ implemented by this circuit?

Figure $1.$ A CMOS$/$transmission$-$gate hybrid circuit

$2).$ Design a falling$-$edge triggered D flip$-$flop using two $2-$to$-1$ MUXes and one inverter, show your design and explain its working principle.

$3).$ Design a $3-$input XOR gate using NMOS$-$based CPL $($Complementary Pass$-$transistor Logic. $\backslash (\backslash$mathrm$\{$Z$\}=[(\backslash$mathrm$\{$A$\}\backslash )$ xor B$\backslash ()\backslash )$ xor C$\backslash (]\backslash ).$ You need to implement both Z and Z $,$ and use CMOS inverters as buffers to recover the logic level of final outputs. $($Hint: You can use two cascaded CPL XOR$/$XNOR gates$).$