2. (3 points) A 2-input xor gate can be built from my-and, my-or and my-not gates. Construct an xor module in Verilog that realizes the logic function, z-xy' +x'y. Inputs are X and y, and z is the output. Please include your Verilog code and comments. Please include the waveforms of inputs and output of your designed xor module from functional simulation using Quartus II simulator