Question: 2. A computer has a L1 data cache and a L1 instruction cache. The latencies of the different kinds of accesses are as follows: cache

2. A computer has a L1 data cache and a L1

2. A computer has a L1 data cache and a L1 instruction cache. The latencies of the different kinds of accesses are as follows: cache hit 1cycle, cache miss 16 cycles. If the miss rate for instructions is 5% and the miss rate for data is 6%, what is the average memory access time in cycles

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