2. A demultiplexer, also known as data distributor, takes in a single input and distributes over several outputs. A demultiplexer of 2" outputs has n select lines. a. Write a Verilog User Defined Primitive (UDP) to model a 1-to-4 demultiplexer. Demultiplexer b. Use the 1-to-4 demultiplexer designed in 2.a to design a 1-to-8 demultiplexer c. Write a Verilog model that describes a 1-to-8 demultiplexer using Verilog HDL data flow modeling d. Write a test bench and use Modelsim to verify the functionality of D 1 x2" the 1-to-8 demultiplexer models in 2.b and 2.c. DEMUX Select Line 2. A demultiplexer, also known as data distributor, takes in a single input and distributes over several outputs. A demultiplexer of 2" outputs has n select lines. a. Write a Verilog User Defined Primitive (UDP) to model a 1-to-4 demultiplexer. Demultiplexer b. Use the 1-to-4 demultiplexer designed in 2.a to design a 1-to-8 demultiplexer c. Write a Verilog model that describes a 1-to-8 demultiplexer using Verilog HDL data flow modeling d. Write a test bench and use Modelsim to verify the functionality of D 1 x2" the 1-to-8 demultiplexer models in 2.b and 2.c. DEMUX Select Line