$2.$ A digital system$-$on$-$chip in a $1-$V $65$ nm process $($with $50$ nm drawn channel lengths and $\backslash (\backslash$lambda$=25\backslash$mathrm$\{$~nm$\}\backslash ))$ has $950$ million transistors, of which $60$ million are in logic gates and the remainder in memory arrays. The average logic transistor width is $\backslash (12\backslash$lambda $\backslash )$ and the average memory transistor width is $\backslash (4\backslash$lambda $\backslash ).$ The memory arrays are divided into banks and only the necessary bank is activated so the memory activity factor is $0\mathrm{.}02.$ The chip is operating at $1\mathrm{.}5$ GHz $.$ Subthreshold leakage for OFF devices is $\backslash (100\backslash$mathrm$\{$nA$\}/\backslash$mu $\backslash$mathrm$\{$m$\}\backslash )$ for low$-$threshold devices and $\backslash (10\backslash$mathrm$\{$nA$\}/\backslash$mu $\backslash$mathrm$\{$m$\}\backslash )$ for high$-$threshold devices. Gate leakage is $\backslash (5\backslash$mathrm$\{$nA$\}/\backslash$mu $\backslash$mathrm$\{$m$\}\backslash ).$ Junction leakage is negligible. Memories use low leakage devices everywhere. Logic uses low$-$leakage devices in all but $7\backslash \%$ of the paths that are most critical for performance. Estimate the static power consumption. Assume half the transistors are OFF $($contribute subthreshold leakage$)$ and half the transistors are ON $($contribute gate leakage$).[$Marks $10]$