$2.$ Cache Configuration and Simulation

In this problem we will consider several cache designs for a processor implementing the MIPS ISA $[$Note that this has implications needed to answer the below questions$].$ Assume that the block offset is five bits and the index is three bits.

a$.$ What is the cache block size in bytes? words? double words? $(10$pts$)$

b$.$ How many sets does this cache have? $[$Hint: note that both direct$-$mapped and fully$-$associative caches can be considered to have sets.$](5$pts$)$

c$.$ Record both the amount of data and meta$-$data $($in bits$)$ this cache holds if it is direct$-$mapped, two$-$way set associative and four$-$way set$-$associative with the same number of cache sets. Also, assume cache uses write$-$back and writeallocate policies $(15$pts$)$

d$.$ Simulate the direct$-$mapped and four$-$way set associative cache with respect to the following series of memory accesses. In the table below, indicate whether each memory access was a $1)$ hit or a miss and $2)$ provide the reason for each miss. Assume the caches have no valid entries to begin with and use a least$-$recently$-$used $($LRU$)$ replacement policy.$(20$pts$)$

$3)$ Write the valid entries in the final state of each cache using the format $.$ What was the hit rate of each cache?