2. (Completeness) (4 points) Pipelined Processor 2. Bowser and Yoshi want to reimplement Mario Kart to run on a pipelined processor. The current version runs on a single cycle CPU with a CPI=1. They take the single cycle CPU which has an IF stage of 500 ps, a RF stage of 250 ps, an EX stage of 200 ps, a M stage of 500 ps and a W stage of 100 ps) They intend to implement a 5 stage pipeline (IF, RF, EX, M, W) based on the single cycle design. Assume they have to introduce flip-flops (registers) between stages and that the overhead (clock skew and setup and Tclock-q) is 50 ps. a) What is the maximum operating frequency of the single cycle processor (to the nearest MHz)? b) What is the maximum operating frequency of the pipelined processor? c) The Mario Kart game needs to run on a portable device which has limited power. The original single cycle CPU runs the game in 100 seconds. What is the average CPI that the pipelined processor must meet if it is to achieve the same performance as the single cycle CPU. Assume the pipelined processor runs at 1.2 GHz