$2.$ Consider designing a cache in a system that uses $64-$bit words for floating point computations. The system details are as follows.

$400$ MHz CPU, $50$ MHz bus speed $(8$ CPU clocks $=1$ bus clock$).$

$$ Cache block size $4$ words.

$$ Bus takes $6$ cycles to transfer the first data chunk and the rest are transferred at a burst rate of $1$ data chunk per cycle.

$$ Bus width is $16$ bits $(16$ bits transferred per bus clock during burst rate$)$

$$ Hit Time $=1$ CPU cycle.

$$ Data cache Miss Rate $=6\%$

a$)$ Considering only data accesses, what is the average memory access time for this system in CPU clock cycles? $(10)$

b$)$ Which speedup would be greater between the following $2$ options if nothing else were changed? Show all your calculations. $(15)$

$$ Doubling bus width to $32-$bits

$$ Increasing the bus speed and memory access time to support a $100$ MHz bus clock speed. $($This means that the number of bus clocks for a cache miss would remain constant, but will be done twice as fast$).$