2. Consider the single cycle processor diagram: Control MemtoReg Unit MemWrite Branch 00 CLK A PCSrc...

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2. Consider the single cycle processor diagram: Control MemtoReg Unit MemWrite Branch 00 CLK A PCSrc ALUControl20 31:26 Op ALUSrc 5:0 Funct RegDst RegWrite CLK CK WE 25:21 A1 WE3 SrcA Zero RD1 RD Instr ALUResult ReadData Instruction 20:16 A2 RD2 SrcB Memory A3 Register WriteData A RD Data Memory WD WD3 File 20:16 15:11 WriteReg4:0 PCPlus4 Signlmm 15:0 < < <2 Sign Extend PCBranch Result Add support for the blt (branch less than) instruction. There is an additional output from the Control Unit, BranchType, which is 1 if the instruction is beq and 0 if the instruction is blt. All other instructions must work as normal. Add additional circuitry as needed. Inst. RegWrite RegDst ALUSrc Branch BranchType MemWrite MemToReg ALUOp add 1 1 0 0 0 0 addi 1 0 1 0 0 0 lw 1 0 1 0 0 1 SW beq blt 0 - 1 0 1 - 0 0 1 1 0 28885 00 00 0 2. Consider the single cycle processor diagram: Control MemtoReg Unit MemWrite Branch 00 CLK A PCSrc ALUControl20 31:26 Op ALUSrc 5:0 Funct RegDst RegWrite CLK CK WE 25:21 A1 WE3 SrcA Zero RD1 RD Instr ALUResult ReadData Instruction 20:16 A2 RD2 SrcB Memory A3 Register WriteData A RD Data Memory WD WD3 File 20:16 15:11 WriteReg4:0 PCPlus4 Signlmm 15:0 < < <2 Sign Extend PCBranch Result Add support for the blt (branch less than) instruction. There is an additional output from the Control Unit, BranchType, which is 1 if the instruction is beq and 0 if the instruction is blt. All other instructions must work as normal. Add additional circuitry as needed. Inst. RegWrite RegDst ALUSrc Branch BranchType MemWrite MemToReg ALUOp add 1 1 0 0 0 0 addi 1 0 1 0 0 0 lw 1 0 1 0 0 1 SW beq blt 0 - 1 0 1 - 0 0 1 1 0 28885 00 00 0