$2.$ For an $8086-1$ processor running at $7\mathrm{.}2$MHz in maximum mode with an $8288$ bus controller, $74$LS$373$ address latches, $74$LS$245$ directional data buffers, and $74$LS$244$ control signal buffers, show all interfacing necessary to interface $128$ kiB of RAM starting at address $0$x$60000.$ Show the address decoder, odd$-$ and even$-$bank control, and bus connections. You do not need to draw the processor subsystem from class.