Question: 2. Given the following memory and register contents, the instruction POP (r5,r4, pc} executes in order to return from this interrupt handler. What is

2. Given the following memory and register contents, the instruction POP (r5,r4,

2. Given the following memory and register contents, the instruction POP (r5,r4, pc} executes in order to return from this interrupt handler. What is the address of the instruction which will execute next? Explain why. Register R13 (SP) 0xFFFF FFF1 0xFFFF_FFF9 0xFFFF FFFD Contents 0x2000_0000 EXC_RETURN Code Memory Address 0x2000 0000 0x0000_5133 0x2000 0004 Contents 0x4500 f 0x2000_0008 0xffff_ fff9 0x2000 000c 0x0000 4800 0x2000 0010 0x0000 5000 0x2000 0014 0x0000 5080 0x2000_0018 0x0000_0009 0x2000 001e 0x0000_0087 0x2000_0020 0x0000_1840 0x2000_0024 0x0000 2380 0x2000 0028 0x0100 0000 Return stack 0 (MSP) 0 (MSP) 1 (PSP) Description Return to Handler mode with MSP Return to Thread mode with MSP Return to Thread mode with PSP

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