Question: 2. How many latches will be generated after synthesis? Provide a brief explanation for your answer. library ieee; use ieee.std_logic_1164.all; entity test is port

2. How many latches will be generated after synthesis? Provide a brief

2. How many latches will be generated after synthesis? Provide a brief explanation for your answer. library ieee; use ieee.std_logic_1164.all; entity test is port (a,b,use b: in STD_LOGIC; d out: out std logic); end test; architecture Beh of test is begin process (a, b, use b) begin Heading 1 if (use b='1') then d out

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