2. In the previous problem you solved 4.7 (we also solved a portion of it in class). To summariz we are given latencies (time to complete an operation) for each hardware unit as shown below I-Mem/D- Register mem File Mux ALU Adder gate Read Setup Extend Control 250ps 150ps 25ps 200ps 150ps 5ps One of the problem with the LDUR and STUR is that these instructions require ALU to find the address of the memory One solution is to use a different format for LDUR/STUR: The address of memory is given in the base register (and no constants are allowed). For example, LDUR XI , ?X2] // X2 contains the address of memory Now, we do not need the ALU to find memory address. a). What is b). Trace the datapaths that are activated by the new LDUR instruction (trace datapaths using the the latency for new LDUR/STUR instructions? figure shown below(or Fig. 4.23 from textbook) c). How would you implement our conventional LDUR/STUR instructions that add a constant value to a base register to find an address? 2. In the previous problem you solved 4.7 (we also solved a portion of it in class). To summariz we are given latencies (time to complete an operation) for each hardware unit as shown below I-Mem/D- Register mem File Mux ALU Adder gate Read Setup Extend Control 250ps 150ps 25ps 200ps 150ps 5ps One of the problem with the LDUR and STUR is that these instructions require ALU to find the address of the memory One solution is to use a different format for LDUR/STUR: The address of memory is given in the base register (and no constants are allowed). For example, LDUR XI , ?X2] // X2 contains the address of memory Now, we do not need the ALU to find memory address. a). What is b). Trace the datapaths that are activated by the new LDUR instruction (trace datapaths using the the latency for new LDUR/STUR instructions? figure shown below(or Fig. 4.23 from textbook) c). How would you implement our conventional LDUR/STUR instructions that add a constant value to a base register to find an address