$\mathrm{.}2$ Possible States in Instruction Execution:

$-*$Fetch:$*$ Obtaining the instruction from memory.

$-*$Decode:$*$ Interpretation and preparation of the fetched instruction.

$-*$Execute:$*$ Performing the operation specified by the instruction.

$-*$Memory Access:$*$ If required, accessing the system's memory.

$-*$Write Back:$*$ Storing the result back to the designated location.

$3\mathrm{.}3$ Approaches to Dealing with Multiple Interrupts:

$-*$Disable Interrupts:$*$ Temporarily halting the processing of interrupts to handle one at a time.

$-*$Priority Scheme:$*$ Assigning priorities to interrupts, allowing the processor to address higher$-$priority interrupts first.

$3\mathrm{.}4$ Types of Transfers in a Computer's Interconnection Structure:

$-*$Read Data Transfer:$*$ Moving data from a source to a destination.

$-*$Write Data Transfer:$*$ Sending data from a source to a destination.

$-*$Control Transfer:$*$ Managing and coordinating operations among different components.

$3\mathrm{.}5$ QPI Protocol Layers:

$-*$Physical Layer:$*$ Concerned with the electrical and mechanical aspects of data transmission.

$-*$Link Layer:$*$ Manages the reliable transmission of data between two points.

$-*$Protocol Layer:$*$ Establishes rules and conventions for communication.

$3\mathrm{.}6$ PCIe Protocol Layers:

$-*$Physical Layer:$*$ Encompasses the electrical and mechanical aspects of data transmission.

$-*$Data Link Layer:$*$ Ensures reliable point$-$to$-$point communication.

$-*$Transaction Layer:$*$ Manages data transactions between devices.