$2.$ Recall that the ARM$7$ processor uses a $3-$stage pipeline and the MIPS processor uses a $5-$stage

pipeline. What is the theoretical minimum number of clock cycles required to execute a group of

twenty$-$one independent arithmetic$/$logic instructions on each processor?

a$)(5)$ Clock cycles required on the ARM$7$ processor $=\_\_\_\_\_\_\_\_$

b$)(5)$ Clock cycles required on the MIPS processor $=\_\_$