2. We held a general discussion about binary codes in class and, specifically, discussed the 8421 code also known as binary coded decimal or BCD. For this question you are to implement a 4-digit BCD adder (a) (20 points) Create a design for a 4-digit unsigned BCD adder. Your written de- sign shoukd include a top level block diagram, second level block diagram showing each single digit adder and the connected carries, and a detailed design of a single digit adder. Note, this is expressly hierarchical in nature; if you choose an alter- native implementation your design must be detailed enough to support a Verilog implementation 1(2) ECE310 Homework 4 Spring 2019 (b) (20 points) Write a Verilog implementation of the design you created in part (a) Submit the Verilog to the Moodle assignment. The requirements for the implemen- tation are listed below 1. The module name must be hw4.q2b 2. There must be 3 input ports: two 16bit (4-digit) inputs A and B, a single bit input C (for the carry) 3. There must be a single output port: a single 17-bit output S for the complete sum (4 digits and a carry). 4. You may use as many files as necessary to implement your design. 5. You may use any adder that we have implemented to date as the underpinning 6. You may use the Verilog posted for the lecture as a starting point; understand 7. You may implement the Verilog as structural, gate-level structural, dataflow (c) (10 points) Prepare and submit a test bench that instantiates the BCD adder from adder that it does not have the correct module name. procedural, or ny mix of the four part (b) and stimulates with at east 15 input vectors. The roquirements for the test bench are below 1. The module name must be hw4.q2c. 2. The test bench must instantiate the hw4.q2b module using the formal/actual (or dot) notation (eg. .A(stimA), etc.) 3. The test bench must stimulate the DUT with at least 15 unique input vectors. . The test bench must print simulation output for each of the input vectors 2. We held a general discussion about binary codes in class and, specifically, discussed the 8421 code also known as binary coded decimal or BCD. For this question you are to implement a 4-digit BCD adder (a) (20 points) Create a design for a 4-digit unsigned BCD adder. Your written de- sign shoukd include a top level block diagram, second level block diagram showing each single digit adder and the connected carries, and a detailed design of a single digit adder. Note, this is expressly hierarchical in nature; if you choose an alter- native implementation your design must be detailed enough to support a Verilog implementation 1(2) ECE310 Homework 4 Spring 2019 (b) (20 points) Write a Verilog implementation of the design you created in part (a) Submit the Verilog to the Moodle assignment. The requirements for the implemen- tation are listed below 1. The module name must be hw4.q2b 2. There must be 3 input ports: two 16bit (4-digit) inputs A and B, a single bit input C (for the carry) 3. There must be a single output port: a single 17-bit output S for the complete sum (4 digits and a carry). 4. You may use as many files as necessary to implement your design. 5. You may use any adder that we have implemented to date as the underpinning 6. You may use the Verilog posted for the lecture as a starting point; understand 7. You may implement the Verilog as structural, gate-level structural, dataflow (c) (10 points) Prepare and submit a test bench that instantiates the BCD adder from adder that it does not have the correct module name. procedural, or ny mix of the four part (b) and stimulates with at east 15 input vectors. The roquirements for the test bench are below 1. The module name must be hw4.q2c. 2. The test bench must instantiate the hw4.q2b module using the formal/actual (or dot) notation (eg. .A(stimA), etc.) 3. The test bench must stimulate the DUT with at least 15 unique input vectors. . The test bench must print simulation output for each of the input vectors